Accessible from P元 (Monitor mode) only when SCR.NS=1.There is no statement about whether or not it can be accessed from P元 monitors.
#Eon timer 1.6 for 64 bit software#
It can be read by secure PL1 software with no hindrances as well. Attempts to access CNTPCT from PL0 when CNTKCTL.PL0CTEN=0 will trigger an #UNDEFINED exception.ĬNTPCT is logically meant to be read by PL2 hypervisors when they need to read a timestamp value. Is only accessible from PL0 modes if CNTKCTL.PL0CTEN is set to 1.However, if hypervisor extensions are supported accesses to CNTPCT will generate a hyp-trap from PL1 unless CNTHCTL.PL1PCTEN is set to 1. Use ISB to ensure that CNTPCT reads are executed in order.
CNTKCTL.PL0PCTEN enables CNTFREQ to be read from secure and non-secure PL0. The CNTFREQ register is only writeable by secure PL1 mode software, and must be initialized to state the frequency of the system upcounter, in Hz.ĬNTFREQ is readable by PL2, secure and non-secure PL1 by default. PL1PCEN enables/disables access to the phyisical timer registers (CNTP_CTL, CNTP_TVAL, CNTP_CVAL) from non-secure PL1 and PL0 mode.Bit PL1PCTEN enables/disables access to CNTPCT from non-secure PL1 and PL0 modes.Bits EVENTEN, EVENTDIR and EVENTI enable and control the direction and bit-position of the bit that triggers the events generated by the virtual counter (CNTVCT).Įnables PL2 software to control access to the counters and timers from non-secure PL1 and PL0 modes.Bit PL0VTEN enables/disables access to CNTV_CTL, CNTV_CVAL and CNTV_TVAL from PL0 modes.Bit PL0PTEN enables/disables access to CNTP_CTL, CNTP_CVAL and CNTP_TVAL from PL0 modes.Bits PL0PCTEN and PL0VCTEN enable/disable access to CNTVCT, CNTPCT and CNTFREQ from PL0 modes.The physical and virtual upcounters as well as the timer registers are architecturally configurable.Įnables PL1 software to control access to the counters and timers from PL0 modes. The controls include enabling/disabling the syscounter, setting the syscounter's value, changing the syscounter's frequency and multiplier, and enabling/disabling halt-on-debug, so that a debugger can halt the syscounter when a processor enters halting debug-mode. The control registers for the system counter are not accessible as coprocessor interface registers, and are only accessible through a memory mapped interface. The syscounter must be implemented in the always-on power domain.Īll agents (including devices in the system other than the host processors) reading the syscounter must be presented with a uniform view of the passage of time.The syscounter is architecturally specified to begin counting from 0 at #RESET.The use of clock multiplication must not change the drift behaviour of the sysupcounter. Clock drift is not required to be at any level of accuracy, but ARM RECOMMENDS that drift be not greater than 10 seconds per 24 hours.Roll-over time is guaranteed to be at least 40 years.The underlying crystal's frequency may change dynamically at runtime. I.e, the hardware crystal may operate at a lower frequency than the frequency claimed by the platform, and a multiplier may applied to the readout value to present the illusion of operation at a higher frequency. Supports clock multiplication to save power.The syscounter increments at a fixed frequency, with architecturally supported ranges being from 1-50 MHz.Any read from the syscounter, physcounter or virtcounter is zero-extended to 64 bits. The GT's syscounter is specified to present the following behaviour to software: The feature also specifies a set of 4 timers per CPU which base their operation on these two upcounters: This is the value of the physical timer, minus a 64-bit virtual offset (CNTVOFF). Virtual upcounter readout ("virtcounter").This is read as a 64-bit read using the CNTPCT register. Physical upcounter readout ("physcounter").This upcounter can be read in two forms, and these readout-forms are logically distinct from the actual value of the syscounter (though the physcounter will usually reflect the syscounter exactly): The feature is specified to provide a system-wide timestamp-counter (henceforth, "syscounter") reference which operates independent of the CPU clock's frequency, allowing for TSC measurements which are invariant over time, regardless of processor scaling, power state and throttling. The ARM Generic Timers (henceforth, "GT") are architecturally specified in ARMv7 as an OPTIONAL extension to the ARMv7-a and ARMv7-r streams. 3.3 Security extensions and hypervisor extensions implemented.